;============================================================================; ; FILENAME: ESCC_I2.ASM ; ; ; ; This program sends a message to the terminal through the following path: ; ; tx_buff -------> ESCC Tx -------> ESCC Rx -------> rx_buff --------> ASCI1 ; ; Interrupt loopback Interrupt RST 20h ; ; ; ; The interrupt here is Z8S180's INT0, mode 2. ; ; ; ; You can choose either channel A or channel B, SDLC or Async, ESCC or SCC. ; ; When SCC is chosen the FIFO will be filled and emptied one byte at a time. ; ; When ESCC is chosen, the FIFO will be filled and emptied 4 bytes a time. ; ; ; ; Interrupt mode 2 of Z180 is used here. When interrupt occurs, pin /INT is ; ; asserted and the lower byte of the interrupt vector is fed in the data bus ; ; while the higher byte of the interrupt vector is retrieved from "i" reg. ; ;----------------------------------------------------------------------------; ; HISTORY: ; ; ; ; 03/02/1999 James Liu Original code with detail comments. ; ;----------------------------------------------------------------------------; ; PLATFORM: Z8S180 Evaluation Board ; ; ; ; TERMINAL SETUP: ; ; ; ; * 57.6 Kbaud, 8-N-2 (8 bits/character, No parity, 2 stop bits). ; ; * Within "ASCII Setup", select "Send line ends with line feeds". ; ; ; ; HARDWARE (Z8S180 Evaluation Board) SETUP: ; ; ; ; * Connect TD1 of P3 to TXA1 of P4. This allows RS232 signal transmits out ; ; through ASCI1 port. ; ; * Connect RD1 of P3 to RXA1 of P4. This allows RS232 incoming signal comes ; ; in from ASCI1 port. ; ; * X1: 18.432 MHz crystal ; ; * U2: 27C512 EPROM with Version 2.7 Debug Monitor. This Debug Monitor will ; ; communicate with terminal through ASCI1 in 57.6 Kbps rate. ; ;----------------------------------------------------------------------------; ; COMPILING AND LINKING THE HEX CODE: ; ; ; ; Use the ZDS (ZiLOG Developer Studio Ver 2.00 Beta 2 or later version) to ; ; generate the hex code "escc_dma.hex". ; ;----------------------------------------------------------------------------; ; MONITOR: ZiLOG 80180 Monitor Version 2.7 (U2 of the Z8S180 board) ; ; ; ; HELP: Type "H". ; ; ; ; LOADING THE HEX CODE: ; ; ; ; Use the "L" command of the Debug Monitor, and the "Send text file" command ; ; of the terminal, to transfer the hex code from the terminal to the Z8S180. ; ; ; ; EXECUTING THE HEX CODE: ; ; ; ; Type "G 8100" with the Debug Monitor to execute the hex code. ; ;----------------------------------------------------------------------------; ; MEMORY MAP: ; ; ; ; 0000 - 7FFF: EPROM (U2:27C512) for Debug Monitor. ; ; 8000 - 80FF: RAM (U3:62256) reserved for Debug Monitor. ; ; 8100 - FFFF: RAM (U3:62256) for user program. ; ;============================================================================; ; Definitions ; ;============================================================================; CPU = Z180 ; ; include "180def.inc" ; ; ;----------------------------------------------------------------------------; channel_a: equ 001h ; == 1 for ESCC/SCC channel A (Connect W/REQA ; ; to /DREQ0, DTR/REQA to /DREQ1. ; ; == 0 for ESCC/SCC channel B (Connect W/REQB ; ; to /DREQ0, DTR/REAB to /DREQ1. ; ;----------------------------------------------; sdlc: equ 001h ; == 1 for SDLC ; ; == 0 for Async ; ;----------------------------------------------; escc: equ 001h ; == 1 for ESCC (85230) ; ; == 0 for SCC (85C30) ; ;----------------------------------------------------------------------------; ; ESCC/SCC registers on 180 Evaluation board ; if channel_a ; ; escc_cont: equ 0C2h ; Channel A pointers ; escc_data: equ 0C3h ; ; else ; ; escc_cont: equ 0C0h ; Channel B pointers ; escc_data: equ 0C1h ; ; endif ; ; ;============================================================================; ; Code segment ; ;============================================================================; ; Initialization ; ;----------------------------------------------------------------------------; org 8100h ; Code start from address 8100 hex ; start: ;----------------------------------------------; ld sp,top_of_stack ; Initialize stack pointer ; ; ; call clear_rx_buff ; Clear Rx buffer ; call init_int_vector ; Initialize interrupt vectors ; call init_escc ; Initialize ESCC ; ; ; ld hl,tx_buff ; Initialize transmit pointer ; ld ix,rx_buff ; Initialize receive pointer ; ; ; xor a,a ; ; ld (escc_status),a ; Clear status ; ; ; ; 00xx xxxx --- escc_status register ; ; |||| ||||_ Tx ends without error ; ; |||| |||__ Tx ends with error ; ; |||| ||___ Rx ends without error ; ; |||| |____ Rx ends with error ; ; ||||______ Overrun during Rx ; ; |||_______ Something wrong ; ; ||________ Not used ; ; ; ;----------------------------------------------; call send_1st_byte ; Send 1st byte to create interrupt to send ; ; the rest of data in the interrupt routine. ; ; ; ei ; Enable interrupts ; loop: ;----------------------------------------------; ld a,(escc_status) ; Wait until receive end. ; and 00001100b ; ; or a ; ; jr z,loop ; ; ;----------------------------------------------; call print_rx_buff ; Print rx_buff to terminal ; rst 28h ; Go back to the Debug Monitor ; ;============================================================================; ; Routines ; ;----------------------------------------------------------------------------; ; Initialize interrupt vectors (INT0 MODE 2) ; ;----------------------------------------------------------------------------; init_int_vector: ; ; ld a,HIGH interrupt_vector_table ; ; ld i,a ; Load high byte of interrupt table to "i" ; ld a,LOW interrupt_vector_table ; ; out0 (il),a ; For safty, load the low byte to "il" ; im 2 ; Set the Z8S180 interrupt in mode 2. ; ret ; ; ;----------------------------------------------------------------------------; ; Initialize ESCC ; ;----------------------------------------------------------------------------; init_escc: ; ; ld hl,escc_init_table ; Initialize the ESCC ; ld b,escc_table_length ; ; ld c,escc_cont ; ; otir ; ; ret ; ; ;----------------------------------------------------------------------------; ; Clear Rx buffer, essc_status, and rx_count with 00. ; ;----------------------------------------------------------------------------; clear_rx_buff: ; ; ld bc,buff_length ; Length of block. ; ld de,rx_buff ; Beginning of destination block. ; ld hl,temp ; Beginning of source block. ; ld (hl),00h ; ; clear_loop: ; ; ldi ; ; ret nv ; Return if completed ; dec hl ; ; jr clear_loop ; ; ;----------------------------------------------------------------------------; ; Output rx_buff to terminal ; ;----------------------------------------------------------------------------; print_rx_buff: ; ; ld hl,rx_buff ; Print rx_buff to terminal ; ld b,6 ; ; rst 20h ; ; ret ; ; ;----------------------------------------------------------------------------; ; Enable ESCC transmit ; ;----------------------------------------------------------------------------; send_1st_byte: ; ; ;----------------------------------------------; ld a,5 ; Enable Tx. ; out (escc_cont),a ; ; ld a,01101000b ; 0110 1001 --- WR5 ; out (escc_cont),a ; |||| ||||_ Tx CRC enable ; ; |||| |||__ RTS ; ; |||| ||___ CRC-16/SDLC ; ; |||| |____ Tx enable ; ; ||||______ Send break ; ; |||_______ 00: Tx 5 bits(or less)/character ; ; | 01: Tx 7 bits / character ; ; | 10: Tx 6 bits / character ; ; | 11: Tx 8 bits / character ; ; |_________ DTR ; ; ; ;----------------------------------------------; ld a,(hl) ; Load 1st byte from tx_buff to Tx FIFO. ; out (escc_data),a ; ; inc hl ; Point to next byte. ; ; ; ld a,11000000b ; Reset EOM latch ; out (escc_cont),a ; ; ; 1100 0000 --- WR0 ; ; ||| ||_|_ Register pointer ; ; |||__|____ 000: Null command ; ; || 001: Point high ; ; || 010: Reset ext/stat interrupts ; ; || 011: Send ABORT (SDLC) ; ; || 100: Enable int. on next Rx char. ; ; || 101: Reset Tx interrupt pending ; ; || 110: Error reset ; ; || 111: Reset highest IUS ; ; ||________ 00: Null command ; ; 01: Reset Rx CRC checker ; ; 10: Reset Tx CRC generator ; ; 11: Reset Tx underrun/EOM latch ; ret ; ; ;============================================================================; ; Interrupt service routines ; ;----------------------------------------------------------------------------; ; Null interrupt routine ; ;----------------------------------------------------------------------------; null_isr: ; ; ei ; Enable interrupts. ; ret ; ; ;----------------------------------------------------------------------------; ; Transmit FIFO empty interrupt service routine ; ;----------------------------------------------------------------------------; tx_int: ; Loads rest of the characters from tx_buff to ; ; Tx FIFO, except the 1st byte. Position in ; ; tx_buff is pointed by HL register. ; ;----------------------------------------------; push af ; Save af register ; ;----------------------------------------------; if escc ; ESCC ; ;----------------------------------------------; ; Since the ESCC Tx FIFO is 4 bytes deep, and ; ld c,4 ; we set WR7':D5=1 to generate transmit ; ; interrupt only when the whole Tx FIFO is ; ; empty,we transfer tx_buff to Tx FIFO 4 bytes ; ; a time. ; load_tx_fifo: ; ; ld a,(escc_status) ; 00xx xxxx --- escc_status register ; ; |||| ||||_ Tx ends without error ; ; |||| |||__ Tx ends with error ; ; |||| ||___ Rx ends without error ; ; |||| |____ Tx ends with CRC error ; ; ||||______ Overrun during Rx ; ; |||_______ Something wrong ; ; ||________ Not used ; ; ; bit 0,a ; If last character is sent, next frame. ; jr nz,next_frame ; ; ; ; ld a,(hl) ; Load a character ; out (escc_data),a ; Load the character into the Tx FIFO. ; inc hl ; Point to next character. ; dec c ; ; jr nz,load_tx_fifo ; 4 bytes yet? ; ; ; cp a,0 ; ; jr nz,tx_exit ; If last char is 0, tx ends without error. ; ;----------------------------------------------; else ; SCC ; ;----------------------------------------------; ; Since the SCC Tx FIFO is only 1 byte deep; ; ; therefore, we send 1 byte a time. ; ; ; ld a,(escc_status) ; 00xx xxxx --- escc_status register ; ; |||| ||||_ Tx ends without error ; ; |||| |||__ Tx ends with error ; ; |||| ||___ Rx ends without error ; ; |||| |____ Tx ends with CRC error ; ; ||||______ Overrun during Rx ; ; |||_______ Something wrong ; ; ||________ Not used ; ; ; ; ; bit 0,a ; If last character is sent, next frame. ; jr nz,next_frame ; ; ; ; ld a,(hl) ; Load a character ; out (escc_data),a ; Load the character into the Tx FIFO. ; inc hl ; Point to next character. ; cp a,0 ; ; jr nz,tx_exit ; If char is 0, tx ends without error. ; ;----------------------------------------------; endif ; endif escc ; ;----------------------------------------------; eom: ; ; ld a,(escc_status) ; To indicate Tx ends without error. ; set 0,a ; ; ld (escc_status),a ; 00xx xxxx --- escc_status register ; ; |||| ||||_ Tx ends without error ; ; |||| |||__ Tx ends with error ; ; |||| ||___ Rx ends without error ; ; |||| |____ Tx ends with CRC error ; ; ||||______ Overrun during Rx ; ; |||_______ Something wrong ; ; ||________ Not used ; ; ; jr tx_exit ; ; ; ; ;----------------------------------------------; next_frame: ; ; ;-----------------------------------------------------------------------; ; You can send another frame here, but this sample code sends only one ; ; frame. ; ; ; ; ; ; ; ;-----------------------------------------------------------------------; ld a,00101000b ; Write to WR0 to reset Tx interrupt pending ; out (escc_cont),a ; ; ; 00xx x000 --- WR0 ; ; ||| ||_|_ Register pointer ; ; |||__|____ 000: Null command ; ; || 001: Point high ; ; || 010: Reset ext/stat interrupts ; ; || 011: Send ABORT (SDLC) ; ; || 100: Enable int. on next Rx char. ; ; || 101: Reset Tx interrupt pending ; ; || 110: Error reset ; ; || 111: Reset highest IUS ; ; ||________ 00: Null command ; ; 01: Reset Rx CRC checker ; ; 10: Reset Tx CRC generator ; ; 11: Reset Tx underrun/EOM latch ; tx_exit: ;----------------------------------------------; ld a,00111000b ; Write to WR0 to reset highest IUS ; out (escc_cont),a ; ; ; 00xx x000 --- WR0 ; ; ||| ||_|_ Register pointer ; ; |||__|____ 000: Null command ; ; || 001: Point high ; ; || 010: Reset ext/stat interrupts ; ; || 011: Send ABORT (SDLC) ; ; || 100: Enable int. on next Rx char. ; ; || 101: Reset Tx interrupt pending ; ; || 110: Error reset ; ; || 111: Reset highest IUS ; ; ||________ 00: Null command ; ; 01: Reset Rx CRC checker ; ; 10: Reset Tx CRC generator ; ; 11: Reset Tx underrun/EOM latch ; ; ; pop af ; Restore af register ; ei ; Enable interrupts ; ret ; ; ;----------------------------------------------------------------------------; ; Receive interrupt service routine ; ;----------------------------------------------------------------------------; rx_int: ; Move received characters from Rx FIFO to ; ; rx_buff. Position in rx_buff is pointed by ; ; IX register. ; ;----------------------------------------------; ; Move 4 bytes from rx_fifo to rx_buff. ; ; Position in rx_buff is pointed by ix. ; ;----------------------------------------------; push af ; Save af register ; ;----------------------------------------------; if escc ; ESCC ; ;----------------------------------------------; ; Since the ESCC Rx FIFO is 8 bytes deep, and ; ld c,4 ; we set WR7':D3=1 to generate receive ; ; interrupt when Rx FIFO is half full - ; ; 4 bytes, we transfer Rx FIFO to rx_buff ; ; 4 bytes a time. ; ; ; ; However,if the last byte is not the 4th byte ; ; in the Rx FIFO,the last interrupt will never ; ; be generated for ASYNC. The correct way to ; ; deal with the situation is to use a timer to ; ; make sure we won't wait the last interrtupt ; ; forever. In this sample code, I do not use ; ; a timer. I stuff 0's to make sure the last ; ; byte received will always be the 4th byte in ; ; the Rx FIFO; therefore, the last interrupt ; ; will be generated. ; ; ; ; Another way to avoid the trouble in ASYNC ; ; mode is to set WR7':D3=0 to generate receive ; ; interrupt for every byte received, just like ; ; the SCC. ; read_rx_fifo: ; ; in a,(escc_data) ; Read a byte from Rx FIFO. ; ld (ix),a ; Save it to rx_buff. ; inc ix ; Point to next location of rx_buff. ; ; ; dec c ; ; jr nz,read_rx_fifo ; If received 4 bytes, go to rx_exit. ; ;----------------------------------------------; else ; SCC ; ;----------------------------------------------; ; Since the receive interrupt occurs everytime ; ; a type is received, we transfer Rx FIFO to ; ; rx_buff 1 byte a time. ; ; ; in a,(escc_data) ; Read a byte from Rx FIFO. ; ld (ix),a ; Save it to rx_buff. ; inc ix ; Point to next location of rx_buff. ; ;----------------------------------------------; endif ; endif escc ; ;----------------------------------------------; cp a,0 ; If the last char is 0, receive finished. ; jr nz,rx_exit ; ; ; ; ld a,(escc_status) ; Set the receive_finish_without_error bit. ; set 2,a ; ; ld (escc_status),a ; 00xx xxxx --- escc_status register ; ; |||| ||||_ Tx ends without error ; ; |||| |||__ Tx ends with error ; ; |||| ||___ Rx ends without error ; ; |||| |____ Tx ends with CRC error ; ; ||||______ Overrun during Rx ; ; |||_______ Something wrong ; ; ||________ Not used ; ; ; rx_exit: ;----------------------------------------------; ld a,00111000b ; Write to WR0 to reset highest IUS ; out (escc_cont),a ; ; ; 00xx x000 --- WR0 ; ; ||| ||_|_ Register pointer ; ; |||__|____ 000: Null command ; ; || 001: Point high ; ; || 010: Reset ext/stat interrupts ; ; || 011: Send ABORT (SDLC) ; ; || 100: Enable int. on next Rx char. ; ; || 101: Reset Tx interrupt pending ; ; || 110: Error reset ; ; || 111: Reset highest IUS ; ; ||________ 00: Null command ; ; 01: Reset Rx CRC checker ; ; 10: Reset Tx CRC generator ; ; 11: Reset Tx underrun/EOM latch ; ; ; pop af ; Restore af register ; ei ; Enable interrupts ; ret ; ; ;----------------------------------------------------------------------------; ; Special condition interrupt service routine ; ;----------------------------------------------------------------------------; special: ; ; ;----------------------------------------------; push af ; Save af register ; ;----------------------------------------------; ld a,1 ; Read RR1 ; out (escc_cont),a ; ; in a,(escc_cont) ; xxxx xxxx --- RR1 ; ; |||| ||||_ All sent ; ; |||| |||__ Residue code 2 ; ; |||| ||___ Residue code 1 ; ; |||| |____ Residue code 0 ; ; ||||______ Parity error ; ; |||_______ Rx overrun error ; ; ||________ CRC/frame error ; ; |_________ End of Frame (SDLC) ; ; ; bit 5,a ; Overrun? ; jr z,eof ; ; ;----------------------------------------------; ld a,(escc_status) ; Error: Over run during receive ; set 4,a ; ; ld (escc_status),a ; 00xx xxxx --- escc_status register ; ; |||| ||||_ Tx ends without error ; ; |||| |||__ Tx ends with error ; ; |||| ||___ Rx ends without error ; ; |||| |____ Tx ends with CRC error ; ; ||||______ Overrun during Rx ; ; |||_______ Something wrong ; ; ||________ Not used ; ; ; ;-----------------------------------------------------------------------; ; If you want to do something with overrun error, put a handler here. ; ; ; ; ; ; ; ; ; ;-----------------------------------------------------------------------; jr sp_exit ; ; ;----------------------------------------------; eof: ; ; bit 7,a ; End of frame? ; jr z,why_error ; ; ; ; bit 6,a ; CRC/frame error? ; jr z,crc_ok ; ; ;----------------------------------------------; ld a,(escc_status) ; Error: CRC/frame error ; set 3,a ; ; ld (escc_status),a ; 00xx xxxx --- escc_status register ; ; |||| ||||_ Tx ends without error ; ; |||| |||__ Tx ends with error ; ; |||| ||___ Rx ends without error ; ; |||| |____ Tx ends with CRC error ; ; ||||______ Overrun during Rx ; ; |||_______ Something wrong ; ; ||________ Not used ; ; ; jr crc_exit ; ; ;----------------------------------------------; crc_ok: ; ; ld a,(escc_status) ; No error: Receive complete without error ; ; set 2,a ; ; set 7,a ; ; ld (escc_status),a ; 00xx xxxx --- escc_status register ; ; |||| ||||_ Tx ends without error ; ; |||| |||__ Tx ends with error ; ; |||| ||___ Rx ends without error ; ; |||| |____ Tx ends with CRC error ; ; ||||______ Overrun during Rx ; ; |||_______ Something wrong ; ; ||________ Not used ; ; ; ;-----------------------------------------------------------------------; ; If you want to check residue code, check it here. ; ; ; ; ; ; ; ; ; ;-----------------------------------------------------------------------; crc_exit: ; Save the 2nd CRC byte to rx_buff. ; in a,(escc_data) ; ; ld (ix),a ; ; inc ix ; ; jr sp_exit ; ; ;----------------------------------------------; why_error: ; ; ld a,(escc_status) ; Error: Something wrong, since we didn't ; set 5,a ; enable parity. ; ld (escc_status),a ; 00xx xxxx --- escc_status register ; ; |||| ||||_ Tx ends without error ; ; |||| |||__ Tx ends with error ; ; |||| ||___ Rx ends without error ; ; |||| |____ Tx ends with CRC error ; ; ||||______ Overrun during Rx ; ; |||_______ Something wrong ; ; ||________ Not used ; ; ; ;----------------------------------------------; sp_exit: ; ; ld a,00111000b ; Write to WR0 to reset highest IUS ; out (escc_cont),a ; ; ; 00xx x000 --- WR0 ; ; ||| ||_|_ Register pointer ; ; |||__|____ 000: Null command ; ; || 001: Point high ; ; || 010: Reset ext/stat interrupts ; ; || 011: Send ABORT (SDLC) ; ; || 100: Enable int. on next Rx char. ; ; || 101: Reset Tx interrupt pending ; ; || 110: Error reset ; ; || 111: Reset highest IUS ; ; ||________ 00: Null command ; ; 01: Reset Rx CRC checker ; ; 10: Reset Tx CRC generator ; ; 11: Reset Tx underrun/EOM latch ; ; ; pop af ; Restore af register ; ei ; Enable interrupts ; ret ; ; ;----------------------------------------------------------------------------; ; External/Status interrupt service routine ; ;----------------------------------------------------------------------------; ext_stat: ; ; ;----------------------------------------------; push af ; Save af register ; ;-----------------------------------------------------------------------; ; If you want something for ext/stat interrupt, put handler here. ; ; ; ; ; ; ; ; ; ;-----------------------------------------------------------------------; ld a,00010000b ; Write to WR0 to reset ext/stat interrupt ; out (escc_cont),a ; ; ; 00xx x000 --- WR0 ; ; ||| ||_|_ Register pointer ; ; |||__|____ 000: Null command ; ; || 001: Point high ; ; || 010: Reset ext/stat interrupts ; ; || 011: Send ABORT (SDLC) ; ; || 100: Enable int. on next Rx char. ; ; || 101: Reset Tx interrupt pending ; ; || 110: Error reset ; ; || 111: Reset highest IUS ; ; ||________ 00: Null command ; ; 01: Reset Rx CRC checker ; ; 10: Reset Tx CRC generator ; ; 11: Reset Tx underrun/EOM latch ; ; ; ld a,00111000b ; Write to WR0 to reset highest IUS ; out (escc_cont),a ; ; ; 00xx x000 --- WR0 ; ; ||| ||_|_ Register pointer ; ; |||__|____ 000: Null command ; ; || 001: Point high ; ; || 010: Reset ext/stat interrupts ; ; || 011: Send ABORT (SDLC) ; ; || 100: Enable int. on next Rx char. ; ; || 101: Reset Tx interrupt pending ; ; || 110: Error reset ; ; || 111: Reset highest IUS ; ; ||________ 00: Null command ; ; 01: Reset Rx CRC checker ; ; 10: Reset Tx CRC generator ; ; 11: Reset Tx underrun/EOM latch ; ; ; pop af ; Restore af register ; ei ; Enable interrupts ; ret ; ; ;============================================================================; ; Data segment ; ;============================================================================; ; ESCC initialization table ; ;----------------------------------------------------------------------------; escc_init_table: ; ; ;----------------------------------------------------------------------------; if sdlc ; SDLC: DMA, NRZ, CRC, 8 bits/character, no ; ; DPLL, PCLK->BRG, baudrate = 1/4 PCLK, ; ; local loop-back. ; ;----------------------------------------------; clockHz: EQU 18432000 ; PLCK = 18.432 MHz ; baudRate: EQU 1024000 ; Data rate = 1.024 Mbps ; ; (It takes time to stuff the Tx ; ; FIFO. This code has not been ; ; optimized to work faster than ; ; 1.024 Mbaud. If the processor ; ; is faster, the data rate can ; ; reach 1/4 of PCLK, 4.608 Mbaud.) ; DPLL: EQU 1 ; 1: DPLL is not used ; ; 16: DPLL with FM0, or FM1 ; ; 32: DPLL with NRZI ; time_const: EQU clockHz/baudRate/DPLL/2 - 2 ; Time Constant ; ;----------------------------------------------; db 9,11000000b ; Hardware reset both channels ; ; ; ; 1100 0000 --- WR9 ; ; |||| ||||_ VIS ; ; |||| |||__ NV ; ; |||| ||___ DLC ; ; |||| |____ MIE ; ; ||||______ Status high / status low ; ; |||_______ Software INTACK enable ; ; ||________ 00: No reset ; ; 01: Reset channel B ; ; 10: Reset channel A ; ; 11: Hardware reset ; ; ; ;----------------------------------------------; db 4,00100000b ; Select SDLC mode ; ; ; ; 00XX 0000 --- WR4 ; ; |||| ||||_ Parity enable ; ; |||| |||__ Parity Even / Odd ; ; |||| ||___ 00: Sync mode enable ; ; |||| 01: 1 stop bit ; ; |||| 10: 1.5 stop bits ; ; |||| 11: 2 stop bits ; ; ||||______ 00: 8-bit sync character ; ; || 01: 16-bit sync character ; ; || 10: SDLC mode (01111110 flag) ; ; || 11: External sync mode ; ; ||________ 00: Async x1 clock mode ; ; 01: Async x16 clock mode ; ; 10: Async x32 clock mode ; ; 11: Async x64 clock mode ; ; ; ;----------------------------------------------; db 2,LOW interrupt_vector_table ; Interrupt vector base ; ; ; ; 0000 0000 --- WR2 ; ; |_______|_ V7..0 ; ; ; ;----------------------------------------------; db 7,01111110b ; Sync flag, 7E for SDLC ; ; ; ; XXXX XXXX --- WR7 ; ; |_______|_ Sync flag ; ; ; ;----------------------------------------------; db 10,01100000b ; FM0, flag idle, flag on underrun, no loop ; ; mode. ; ; ; ; XXX0 XX00 --- WR10 ; ; |||| ||||_ 6-bit/8-bit sync ; ; |||| |||__ Loop mode ; ; |||| ||___ Abort/flag on underrun ; ; |||| |____ Mark/flag idle ; ; ||||______ Go active on poll ; ; |||_______ 00: NRZ ; ; | 01: NRZI ; ; | 10: FM1 ; ; | 11: FM0 ; ; |_________ CRC preset 1/0 ; ; ; ;----------------------------------------------; db 11,01010110b ; Tx clock = BRG, Rx clock = BRG, ; ; No crystal, /TRxC is BRG output. ; ; ; ; 0XXX X1XX --- WR11 ; ; |||| ||||_ 00: /TRxC out = Xtal output ; ; |||| || 01: /TRxC out = Transmit clock ; ; |||| || 10: /TRxC out = BRG output ; ; |||| || 11: /TRxC out = DPLL output ; ; |||| ||___ 0: /TRxC is input ; ; |||| | 1: /TRxC is output ; ; ||||_|____ 00: Tx clock = /RTxC pin ; ; ||| 01: Tx clock = /TRxC pin ; ; ||| 10: Tx clock = BRG output ; ; ||| 11: Tx clock = DPLL output ; ; |||_______ 00: Rx clock = /RTxC pin ; ; | 01: Rx clock = /TRxC pin ; ; | 10: Rx clock = BRG output ; ; | 11: Rx clock = DPLL output ; ; |_________ 0: /RTxC connects no xtal ; ; 1: /RTxC connects with xtal ; ; ; ;----------------------------------------------; db 12,LOW time_const ; Load "Time Constant" to BRG ; ; ; ; XXXX XXXX --- WR12 ; ; |_______|_ Lower byte of Time Constant ; ; ; db 13,HIGH time_const ; XXXX XXXX --- WR13 ; ; |_______|_ Higher byte of Time Constant ; ; ; ;----------------------------------------------; db 14,00010011b ; Local loopback, PCLK -> BRG, enable BRG. ; ; ; ; 0000 00XX --- WR14 ; ; | || ||||_ BRG enable ; ; | || |||__ BRG source: PCLK / /RTxC ; ; | || ||___ DTR//REQ function select ; ; | || |____ Auto echo ; ; | ||______ Local loop back ; ; |_|_______ 000: Null command ; ; 001: Enter search mode ; ; 010: Reset missing clock ; ; 011: Disable DPLL ; ; 100: DPLL source: BRG ; ; 101: DPLL source: /RTxC ; ; 110: DPLL operates in FM mode ; ; 111: DPLL operates in NRZI mode ; ; ; ;----------------------------------------------; if escc ; ESCC ; ;----------------------------------------------; db 15,00000101b ; Enable WR7' and SDLC FIFO ; ; ; ; 0000 0101 --- WR15 ; ; |||| ||||_ WR7' SDLC feature enable ; ; |||| |||__ Zero count IE ; ; |||| ||___ SDLC FIFO enable ; ; |||| |____ DCD IE ; ; ||||______ Sync/hunt IE ; ; |||_______ CTS IE ; ; ||________ Tx underrun/EOM IE ; ; |_________ Break / abort IE ; ; ; ;----------------------------------------------; db 7,00101000b ; Enable Tx and Rx FIFO enhancements ; ; ; ; 0010 1000 --- WR7' ; ; |||| ||||_ Auto Tx flag ; ; |||| |||__ Auto EOM reset ; ; |||| ||___ Auto /RTS deactivation ; ; |||| |____ Rx FIFO interrupt level ; ; ||||______ /DTR//REQ timing mode ; ; |||_______ Tx FIFO interrupt level ; ; ||________ Extended read enable ; ; |_________ Not used, always 0 ; ; ; ; ; ;----------------------------------------------; endif ; endif ESCC ; ;----------------------------------------------; db 00010000b,00010000b ; Reset ext/stat interrupt twice. ; ; ; ; 0001 0000 --- WR0 ; ; ||| ||_|_ Register pointer ; ; |||__|____ 000: Null command ; ; || 001: Point high ; ; || 010: Reset ext/stat interrupts ; ; || 011: Send ABORT (SDLC) ; ; || 100: Enable int. on next Rx char. ; ; || 101: Reset Tx interrupt pending ; ; || 110: Error reset ; ; || 111: Reset highest IUS ; ; ||________ 00: Null command ; ; 01: Reset Rx CRC checker ; ; 10: Reset Tx CRC generator ; ; 11: Reset Tx underrun/EOM latch ; ; ; db 1,00010011b ; Enable Tx interrupt, ext/stat interrupt ; ; Rx int. on all char. or special condition. ; ; ; ; 0001 0011 --- WR1 ; ; |||| ||||_ Ext interrupt enable ; ; |||| |||__ Tx interrupt enable ; ; |||| ||___ Parity is special condition ; ; ||||_|____ 00: Rx interrupt disable ; ; ||| 01: Rx int on 1st char or special ; ; ||| 10: Rx int on all char or special ; ; ||| 11: Rx int on special only ; ; |||_______ 0: W/REQ on transmit ; ; || 1: W/REQ on receive ; ; ||________ 0: W/REQ as /WAIT ; ; | 1: W/REQ as /REQ for DMA ; ; |_________ enable W/REQ ; ; ; ;----------------------------------------------; db 3,11000001b ; Enable Rx and Rx CRC, Rx 8-bit/character ; ; ; ; 1100 0001 --- WR3 ; ; |||| ||||_ Rx enable ; ; |||| |||__ Sync character load inhibit ; ; |||| ||___ Address search mode (SDLC) ; ; |||| |____ Rx CRC enable ; ; ||||______ Enter hunt mode ; ; |||_______ Auto enables ; ; ||________ 00: Rx 5 bits/character ; ; 01: Rx 7 bits/character ; ; 10: Rx 6 bits/character ; ; 11: Rx 8 bits/character ; ; ; ;----------------------------------------------; db 9,00001001b ; Enable enterrupts, use V7..0 as interrupt ; ; vector, use V3..1 for status. ; ; ; ; 0000 1001 --- WR9 ; ; |||| ||||_ VIS ; ; |||| |||__ NV ; ; |||| ||___ DLC ; ; |||| |____ MIE ; ; ||||______ Status high / status low ; ; |||_______ Software INTACK enable ; ; ||________ 00: No reset ; ; 01: Reset channel B ; ; 10: Reset channel A ; ; 11: Hardware reset ; ; ; ;----------------------------------------------------------------------------; else ; Async: DMA, 8-N-1, x1 clock mode, no CRC, no ; ; DPLL, PCLK->BRG, baudrate = 1/4 PCLK, ; ; local loop-back. ; ;----------------------------------------------; clockHz: EQU 18432000 ; PLCK = 18.432 MHz ; baudRate: EQU 4608000 ; Data rate = 4.608 Mbps ; ; (The maximum baud rate is 1/4 of ; ; PCLK, 4.608 Mbaud.) ; cMode: EQU 1 ; 1: Async x1 clock mode ; ; 16: Async x16 clock mode ; ; 32: Async x32 clock mode ; ; 64: Async x64 clock mode ; time_const: EQU clockHz/baudRate/cMode/2 - 2 ; Time Constant ; ;----------------------------------------------; db 9,11000000b ; Hardware reset both channels ; ; ; ; XX00 0000 --- WR9 ; ; |||| ||||_ VIS ; ; |||| |||__ NV ; ; |||| ||___ DLC ; ; |||| |____ MIE ; ; ||||______ Status high / status low ; ; |||_______ Software INTACK enable ; ; ||________ 00: No reset ; ; 01: Reset channel B ; ; 10: Reset channel A ; ; 11: Hardware reset ; ; ; ;----------------------------------------------; db 4,00000100b ; Async x1 clock, 1 stop bit, parity off ; ; ; ; 00XX 0000 --- WR4 ; ; |||| ||||_ Parity enable ; ; |||| |||__ Parity Even / Odd ; ; |||| ||___ 00: Sync mode enable ; ; |||| 01: 1 stop bit ; ; |||| 10: 1.5 stop bits ; ; |||| 11: 2 stop bits ; ; ||||______ 00: 8-bit sync character ; ; || 01: 16-bit sync character ; ; || 10: SDLC mode (01111110 flag) ; ; || 11: External sync mode ; ; ||________ 00: Async x1 clock mode ; ; 01: Async x16 clock mode ; ; 10: Async x32 clock mode ; ; 11: Async x64 clock mode ; ; ; ;----------------------------------------------; db 2,LOW interrupt_vector_table ; Interrupt vector base ; ; ; ; XXXX 0000 --- WR2 ; ; |_______|_ V7..0 ; ; ; ;----------------------------------------------; db 11,01010110b ; No crystal, /TRxC is BRG output, ; ; Tx clock = BRG, Rx clock = BRG. ; ; ; ; 0XXX X1XX --- WR11 ; ; |||| ||||_ 00: /TRxC out = Xtal output ; ; |||| || 01: /TRxC out = Transmit clock ; ; |||| || 10: /TRxC out = BRG output ; ; |||| || 11: /TRxC out = DPLL output ; ; |||| ||___ /TRxC output / input ; ; ||||_|____ 00: Tx clock = /RTxC pin ; ; ||| 01: Tx clock = /TRxC pin ; ; ||| 10: Tx clock = BRG output ; ; ||| 11: Tx clock = DPLL output ; ; |||_______ 00: Rx clock = /RTxC pin ; ; | 01: Rx clock = /TRxC pin ; ; | 10: Rx clock = BRG output ; ; | 11: Rx clock = DPLL output ; ; |_________ /RTxC xtal / no xtal ; ; ; ;----------------------------------------------; db 12,LOW time_const ; Load "Time Constant" to BRG ; ; ; ; XXXX XXXX --- WR12 ; ; |_______|_ Lower byte of Time Constant ; ; ; db 13,HIGH time_const ; XXXX XXXX --- WR13 ; ; |_______|_ Higher byte of Time Constant ; ; ; ;----------------------------------------------; db 14,00010011b ; Local loopback, PCLK -> BRG, enable BRG. ; ; ; ; 0000 00XX --- WR14 ; ; | || ||||_ BRG enable ; ; | || |||__ BRG source: PCLK / /RTxC ; ; | || ||___ DTR//REQ function select ; ; | || |____ Auto echo ; ; | ||______ Local loop back ; ; |_|_______ 000: Null command ; ; 001: Enter search mode ; ; 010: Reset missing clock ; ; 011: Disable DPLL ; ; 100: DPLL source: BRG ; ; 101: DPLL source: /RTxC ; ; 110: DPLL operates in FM mode ; ; 111: DPLL operates in NRZI mode ; ; ; ;----------------------------------------------; if escc ; ESCC ; ;----------------------------------------------; db 15,00000001b ; Enable WR7'. ; ; ; ; 0000 0101 --- WR15 ; ; |||| ||||_ WR7' SDLC feature enable ; ; |||| |||__ Zero count IE ; ; |||| ||___ SDLC FIFO enable ; ; |||| |____ DCD IE ; ; ||||______ Sync/hunt IE ; ; |||_______ CTS IE ; ; ||________ Tx underrun/EOM IE ; ; |_________ Break / abort IE ; ; ; ;----------------------------------------------; db 7,00101000b ; Enable Tx and Rx FIFO enhancements ; ; ; ; 0010 1000 --- WR7' ; ; |||| ||||_ Auto Tx flag ; ; |||| |||__ Auto EOM reset ; ; |||| ||___ Auto /RTS deactivation ; ; |||| |____ Rx FIFO interrupt level ; ; ||||______ /DTR//REQ timing mode ; ; |||_______ Tx FIFO interrupt level ; ; ||________ Extended read enable ; ; |_________ Not used, always 0 ; ; ; ; ; ;----------------------------------------------; endif ; endif ESCC ; ;----------------------------------------------; db 00010000b,00010000b ; Reset ext/stat interrupt twice. ; ; ; ; 0001 0000 --- WR0 ; ; ||| ||_|_ Register pointer ; ; |||__|____ 000: Null command ; ; || 001: Point high ; ; || 010: Reset ext/stat interrupts ; ; || 011: Send ABORT (SDLC) ; ; || 100: Enable int. on next Rx char. ; ; || 101: Reset Tx interrupt pending ; ; || 110: Error reset ; ; || 111: Reset highest IUS ; ; ||________ 00: Null command ; ; 01: Reset Rx CRC checker ; ; 10: Reset Tx CRC generator ; ; 11: Reset Tx underrun/EOM latch ; ; ; ;----------------------------------------------; db 1,00010011b ; Enable Tx interrupt, ext/stat interrupt ; ; Rx int. on all char. or special condition. ; ; ; ; 0001 0011 --- WR1 ; ; |||| ||||_ Ext interrupt enable ; ; |||| |||__ Tx interrupt enable ; ; |||| ||___ Parity is special condition ; ; ||||_|____ 00: Rx interrupt disable ; ; ||| 01: Rx int on 1st char or special ; ; ||| 10: Rx int on all char or special ; ; ||| 11: Rx int on special only ; ; |||_______ 0: W/REQ on transmit ; ; || 1: W/REQ on receive ; ; ||________ 0: W/REQ as /WAIT ; ; | 1: W/REQ as /REQ for DMA ; ; |_________ enable W/REQ ; ; ; ;----------------------------------------------; db 3,11000001b ; Enable Rx, Rx 8-bit/character. ; ; ; ; 1100 0001 --- WR3 ; ; |||| ||||_ Rx enable ; ; |||| |||__ Sync character load inhibit ; ; |||| ||___ Address search mode (SDLC) ; ; |||| |____ Rx CRC enable ; ; ||||______ Enter hunt mode ; ; |||_______ Auto enables ; ; ||________ 00: Rx 5 bits/character ; ; 01: Rx 7 bits/character ; ; 10: Rx 6 bits/character ; ; 11: Rx 8 bits/character ; ; ; ;----------------------------------------------; db 9,00001001b ; Enable enterrupts, use V7..0 as interrupt ; ; vector, use V3..1 for status. ; ; ; ; 0000 1001 --- WR9 ; ; |||| ||||_ VIS ; ; |||| |||__ NV ; ; |||| ||___ DLC ; ; |||| |____ MIE ; ; ||||______ Status high / status low ; ; |||_______ Software INTACK enable ; ; ||________ 00: No reset ; ; 01: Reset channel B ; ; 10: Reset channel A ; ; 11: Hardware reset ; ; ; ;----------------------------------------------------------------------------; endif ; endif SDLC-Async ; ;----------------------------------------------; escc_table_length: equ $-escc_init_table ; Calculate table length ; ;----------------------------------------------------------------------------; ; Reserve data space ; ;----------------------------------------------------------------------------; tx_buff: ; Reserve Tx buffer ; ;----------------------------------------------; db "\r\n\nThe " ; ; ;----------------------------------------------; if escc ; ESCC ; db "ESCC " ; ; else ; SCC ; db "SCC " ; ; endif ; ; ;----------------------------------------------; if channel_a ; Channel A ; db "channel A " ; ; else ; Channel B ; db "channel B " ; ; endif ; ; ;----------------------------------------------; db "sent and received this message in " ; ;----------------------------------------------; if sdlc ; SDLC ; db "SDLC " ; ; else ; Async ; db "ASYNC " ; ; endif ; ; ;----------------------------------------------; db "mode\r\nwith INTERRUPT transfers in mode 2.\r\n" ; ;----------------------------------------------; buff_length: equ $-tx_buff ; Calculate the length of tx_buff ; ;----------------------------------------------; db 0,0,0,0 ; End with 0's. ; ;----------------------------------------------------------------------------; temp: ; ; ds 1 ; Reserve 1 byte for temp. ; escc_status: ; ; ds 1 ; Reserve 1 byte for escc_status. ; ;----------------------------------------------------------------------------; rx_buff: ; Reserve Rx buffer with same length as Tx ; ds buff_length + 2 ; buffer plus 2 more bytes for CRC. ; ;----------------------------------------------------------------------------; ds 20h ; Reserve at least 20h bytes for stack. ; align 100h ; ; top_of_stack: ; ; ;----------------------------------------------------------------------------; ; Interrupt vector table ; ;----------------------------------------------------------------------------; ; align 100h ; Have to start from address x,0000,0000b ; ;----------------------------------------------; ds 20h ; Reserve 20h bytes for safty, in case the ; ; processor may use them for other interrupts. ; interrupt_vector_table: ; ; ;----------------------------------------------; if channel_a ; Channel A ; ;----------------------------------------------; dw null_isr ; Channal B transmit interrupt ; dw null_isr ; Channal B external/status interrupt ; dw null_isr ; Channal B receive interrupt ; dw null_isr ; Channal B special condition interrupt ; dw tx_int ; Channal A transmit interrupt ; dw ext_stat ; Channal A external/status interrupt ; dw rx_int ; Channal A receive interrupt ; dw special ; Channal A special condition interrupt ; ;----------------------------------------------; else ; Channel B ; ;----------------------------------------------; dw tx_int ; Channal B transmit interrupt ; dw ext_stat ; Channal B external/status interrupt ; dw rx_int ; Channal B receive interrupt ; dw special ; Channal B special condition interrupt ; dw null_isr ; Channal A transmit interrupt ; dw null_isr ; Channal A external/status interrupt ; dw null_isr ; Channal A receive interrupt ; dw null_isr ; Channal A special condition interrupt ; ;----------------------------------------------; endif ; endif channel_a ; ;============================================================================; end start ; End of assembly code ; ;============================================================================;