;============================================================================; ; FILENAME: ESCC_DMA.ASM ; ; ; ; This program sends a message to the terminal through the following path: ; ; tx_buff -------> ESCC Tx -------> ESCC Rx -------> rx_buff --------> ASCI1 ; ; DMA1 loopback DMA0 RST 20h ; ; ; ; You can choose either channel A or channel B, SDLC or Async, ESCC or SCC. ; ; When SCC is chosen the FIFO will be filled and emptied one byte at a time. ; ; When ESCC is chosen, the FIFO will be filled and emptied 4 bytes a time. ; ; ; ; In this full-duplex application, DTR/REQ is configured for transmit and ; ; WAIT/REQ is configured for receive. ; ;----------------------------------------------------------------------------; ; HISTORY: ; ; ; ; 03/02/1999 James Liu Original code with detail comments. ; ;----------------------------------------------------------------------------; ; PLATFORM: Z8S180 Evaluation Board ; ; ; ; TERMINAL SETUP: ; ; ; ; * 57.6 Kbaud, 8-N-2 (8 bits/character, No parity, 2 stop bits). ; ; * Within "ASCII Setup", select "Send line ends with line feeds". ; ; ; ; HARDWARE (Z8S180 Evaluation Board) SETUP: ; ; ; ; * Connect /W//REQA (or /W//REQB) with /DREQ0. This is for DMA0 /REQ. ; ; * Connect /DTR//REQA (or /DTR//REQB) with /DREQ1. This is for DMA1 /REQ. ; ; * Connect TD1 of P3 to TXA1 of P4. This allows RS232 signal transmits out ; ; through ASCI1 port. ; ; * Connect RD1 of P3 to RXA1 of P4. This allows RS232 incoming signal comes ; ; in from ASCI1 port. ; ; * X1: 18.432 MHz crystal ; ; * U2: 27C512 EPROM with Version 2.7 Debug Monitor. This Debug Monitor will ; ; communicate with terminal through ASCI1 in 57.6 Kbps rate. ; ;----------------------------------------------------------------------------; ; COMPILING AND LINKING THE HEX CODE: ; ; ; ; Use the ZDS (ZiLOG Developer Studio Ver 2.00 Beta 2 or later version) to ; ; generate the hex code "escc_dma.hex". ; ;----------------------------------------------------------------------------; ; MONITOR: ZiLOG 80180 Monitor Version 2.7 (U2 of the Z8S180 board) ; ; ; ; HELP: Type "H". ; ; ; ; LOADING THE HEX CODE: ; ; ; ; Use the "L" command of the Debug Monitor, and the "Send text file" command ; ; of the terminal, to transfer the hex code from the terminal to the Z8S180. ; ; ; ; EXECUTING THE HEX CODE: ; ; ; ; Type "G 8100" with the Debug Monitor to execute the hex code. ; ;----------------------------------------------------------------------------; ; MEMORY MAP: ; ; ; ; 0000 - 7FFF: EPROM (U2:27C512) for Debug Monitor. ; ; 8000 - 80FF: RAM (U3:62256) reserved for Debug Monitor. ; ; 8100 - FFFF: RAM (U3:62256) for user program. ; ;============================================================================; ; Definitions ; ;============================================================================; CPU = Z180 ; ; include "180def.inc" ; ; ;----------------------------------------------------------------------------; channel_a: equ 001h ; == 1 for ESCC/SCC channel A (Connect W/REQA ; ; to /DREQ0, DTR/REQA to /DREQ1. ; ; == 0 for ESCC/SCC channel B (Connect W/REQB ; ; to /DREQ0, DTR/REAB to /DREQ1. ; ;----------------------------------------------; sdlc: equ 001h ; == 1 for SDLC ; ; == 0 for Async ; ;----------------------------------------------; escc: equ 001h ; == 1 for ESCC (85230) ; ; == 0 for SCC (85C30) ; ;----------------------------------------------------------------------------; ; ESCC/SCC registers on 180 Evaluation board ; if channel_a ; ; escc_cont: equ 0C2h ; Channel A pointers ; escc_data: equ 0C3h ; ; else ; ; escc_cont: equ 0C0h ; Channel B pointers ; escc_data: equ 0C1h ; ; endif ; ; ;============================================================================; ; Code segment ; ;============================================================================; ; Initialization ; ;----------------------------------------------------------------------------; org 8100h ; Code start from address 8100 hex ; start: ;----------------------------------------------; ld sp,top_of_stack ; Initialize stack pointer ; call init_int_vector ; Initialize interrupt vectors ; call clear_rx_buff ; Clear Rx buffer ; call init_escc ; Initialize ESCC ; call init_dma ; Initialize DMA ; ; ; xor a,a ; ; ld (done_flag),a ; Clear status ; ;----------------------------------------------; call enable_DMA0_DMA1 ; Enable DMA and their interrupts ; call enable_ESCC_Tx ; Enable ESCC Tx ; ; ; ei ; Enable interrupts ; ; ; ld a,(tx_buff) ; Load 1st byte by software, to create an edge ; out (escc_data),a ; for DMA Tx. ; ; ; ; After this point, DMA1 will transfer the ; ; whole tx_buff to ESCC Tx, and the DMA0 will ; ; transfer ESCC Rx to rx_buff automatically. ; ; What need to be done by this code is wait ; ; for the receive done interrupt. ; loop: ;----------------------------------------------; ld a,(done_flag) ; Wait until DMA tx and rx end. ; cp 10000001b ; 10000000b: Receive done. ; jr nz,loop ; 00000001b: Transmit done. ; ;----------------------------------------------; call print_rx_buff ; Print rx_buff to terminal ; rst 28h ; Go back to the Debug Monitor ; ;============================================================================; ; Routines ; ;----------------------------------------------------------------------------; ; Initialize interrupt vectors ; ;----------------------------------------------------------------------------; init_int_vector: ; ; ld hl,interrupt_vector_table ; ; ld a,h ; Load high byte of interrupt table to "i" ; ld i,a ; ; out0 (il),l ; low byte of interrupt table to "il" ; ret ; ; ;----------------------------------------------------------------------------; ; Initialize ESCC ; ;----------------------------------------------------------------------------; init_escc: ; ; ld hl,escc_init_table ; Initialize the ESCC ; ld b,escc_table_length ; ; ld c,escc_cont ; ; otir ; ; ret ; ; ;----------------------------------------------------------------------------; ; Initialize DMA ; ;----------------------------------------------------------------------------; init_dma: ; ; ld hl,dma_init_table ; Initialize DMA ; ld b,dma_table_length ; ; ld c,sar0l ; Start from SAR0L ; otimr ; ; ret ; ; ;----------------------------------------------------------------------------; ; Clear Rx buffer with 00 ; ;----------------------------------------------------------------------------; clear_rx_buff: ; ; ld bc,buff_length ; ; ld de,rx_buff ; ; ld hl,zero ; ; ld (hl),00h ; Set 00h to temp register ; clear_loop: ; ; ldi ; ; ret nv ; Return if completed ; dec hl ; ; jr clear_loop ; ; ;----------------------------------------------------------------------------; ; Output rx_buff to terminal ; ;----------------------------------------------------------------------------; print_rx_buff: ; ; ld hl,rx_buff ; Print rx_buff to terminal ; ld b,6 ; ; rst 20h ; ; ret ; ; ;----------------------------------------------------------------------------; ; Enable ESCC transmit ; ;----------------------------------------------------------------------------; enable_ESCC_Tx: ; ; ld a,5 ; Select WR5 to enable ESCC Tx ; out (escc_cont),a ; ; ld a,01101000b ; 0XX0 1000 --- WR5 ; out (escc_cont),a ; |||| ||||_ Tx CRC enable ; ; |||| |||__ RTS ; ; |||| ||___ CRC-16/SDLC ; ; |||| |____ Tx enable ; ; ||||______ Send break ; ; |||_______ 00: Tx 5 bits(or less)/character ; ; | 01: Tx 7 bits / character ; ; | 10: Tx 6 bits / character ; ; | 11: Tx 8 bits / character ; ; |_________ DTR ; ;----------------------------------------------; ret ; ; ;----------------------------------------------------------------------------; ; Enable DMA0, DMA1 and their interrupts ; ;----------------------------------------------------------------------------; enable_DMA0_DMA1: ; ; ld a,11001100b ; Enable DMA0, DMA1 and their interrupts ; out0 (dstat),a ; ; ; 1100 11XX --- DSTAT ; ; |||| ||||_ DMA enable status, read only ; ; |||| |||__ Not used ; ; |||| ||___ DMA0 interrupt enable ; ; |||| |____ DMA1 interrupt enable ; ; ||||______ Won't change DMA0 ; ; |||_______ Won't change DMA1 ; ; ||________ DMA0 enable, and status ; ; |_________ DMA1 enable, and status ; ret ; ; ;----------------------------------------------------------------------------; ; Disable DMA0 interrupt ; ;----------------------------------------------------------------------------; disable_DMA0: ; ; in0 b,(dstat) ; DMA0 finish? ; bit 6,b ; ; jr nz,dma0_not_done ; ; ; ; ld a,b ; ; and a,11111011b ; Disable DMA0 interrupt ; out0 (dstat),a ; ; ; XXXX X0XX --- DSTAT ; ; |||| ||||_ DMA enable status, read only ; ; |||| |||__ Not used ; ; |||| ||___ DMA0 interrupt enable ; ; |||| |____ DMA1 interrupt enable ; ; ||||______ Won't change DMA0 ; ; |||_______ Won't change DMA1 ; ; ||________ DMA0 enable, and status ; ; |_________ DMA1 enable, and status ; dma0_not_done: ; ; ret ; ; ;----------------------------------------------------------------------------; ; Disable DMA1 interrupt ; ;----------------------------------------------------------------------------; disable_DMA1: ; ; in0 b,(dstat) ; DMA1 finish? ; bit 7,b ; ; jr nz,dma1_not_done ; ; ; ; ld a,b ; ; and a,11110111b ; Disable DMA1 interrupt ; out0 (dstat),a ; ; ; XXXX 0XXX --- DSTAT ; ; |||| ||||_ DMA enable status, read only ; ; |||| |||__ Not used ; ; |||| ||___ DMA0 interrupt enable ; ; |||| |____ DMA1 interrupt enable ; ; ||||______ Won't change DMA0 ; ; |||_______ Won't change DMA1 ; ; ||________ DMA0 enable, and status ; ; |_________ DMA1 enable, and status ; dma1_not_done: ; ; ret ; ; ;============================================================================; ; Interrupt service routines ; ;----------------------------------------------------------------------------; ; Null interrupt routine ; ;----------------------------------------------------------------------------; null_isr: ; ; ei ; ; ret ; ; ;----------------------------------------------------------------------------; ; DMA0 interrupt routine ; ;----------------------------------------------------------------------------; rx_end: ; ; call disable_DMA0 ; Disable DMA0 and its interrupt ; ; ; ld a,(done_flag) ; ; or 10000000b ; Receive done. ; ld (done_flag),a ; ; ; ; ei ; ; ret ; ; ;----------------------------------------------------------------------------; ; DMA1 interrupt routine ; ;----------------------------------------------------------------------------; tx_end: ; ; call disable_DMA1 ; Disable DMA1 and its interrupt, keep DMA0 ; ; interrupt enabled ; ld a,(done_flag) ; ; or 00000001b ; Transmit done. ; ld (done_flag),a ; ; ; ; ei ; ; ret ; ; ;============================================================================; ; Data segment ; ;============================================================================; ; Interrupt vector table ; ;----------------------------------------------------------------------------; ; org code_entry + 200h ; ; align 32 ; Have to start from address xxx00000b ; interrupt_vector_table: ; ; dw null_isr ; /INT1 ; dw null_isr ; /INT2 ; dw null_isr ; PRT0 ; dw null_isr ; PRT1 ; dw rx_end ; DMA0 ; dw tx_end ; DMA1 ; dw null_isr ; CSI/O ; dw null_isr ; ASCI0 ; dw null_isr ; ASCI1 ; dw null_isr ; ; dw null_isr ; ; dw null_isr ; ; dw null_isr ; ; dw null_isr ; ; dw null_isr ; ; dw null_isr ; ; ;----------------------------------------------------------------------------; ; DMA initialization table ; ;----------------------------------------------------------------------------; dma_init_table: ; DMA0 for receive, ESCC -> rx_buff(+1) ; ; DMA1 for transmit, tx_buff(+1) -> ESCC ; ;----------------------------------------------; db escc_data ; sar0l DMA0 source : ESCC ; db 0 ; sar0h ; db 0 ; sar0b ; ;----------------------------------------------; dw rx_buff ; dar0l, dar0h DMA0 destination : rx_buff ; db 0 ; dar0b ; ;----------------------------------------------; dw buff_length ; bcr0l, bcr0h ; ;----------------------------------------------; dw tx_buff+1 ; mar1l, mar1h DMA1 memory : tx_buff ; db 0 ; mar1b (1st byte will be sent manually ; ; to create a /REQ edge) ; ;----------------------------------------------; db escc_data ; iar1l DMA1 I/O : ESCC ; db 0 ; iar1h ; db 0 ; Reserved ; ;----------------------------------------------; dw buff_length-1 ; bcr1l, bcr1h (1st byte will be sent manually ; ; to create a /REQ edge) ; ;----------------------------------------------; db 00000000b ; Disable DMA0, DMA1 and their interrupts ; ; ; ; 0000 0000 --- dstat ; ; |||| ||||_ DMA enable status, read only ; ; |||| |||__ Not used ; ; |||| ||___ DMA0 interrupt enable ; ; |||| |____ DMA1 interrupt enable ; ; ||||______ Won't change DMA0 ; ; |||_______ Won't change DMA1 ; ; ||________ DMA0 enable, and status ; ; |_________ DMA1 enable, and status ; ; ; ;----------------------------------------------; db 00001100b ; DMA0 I/O -> memory+1 ; ; ; ; 0000 1100 --- dmode ; ; |||| ||||_ Not used ; ; |||| |||__ Burst/cycle steal (mem - mem only); ; |||| ||___ DMA0 source ; ; |||| 00: Memory, +1 ; ; |||| 01: Memory, -1 ; ; |||| 10: Memory, fixed ; ; |||| 11: I/O, fixed ; ; ||||______ DMA0 destination ; ; || 00: Memory, +1 ; ; || 01: Memory, -1 ; ; || 10: Memory, fixed ; ; || 11: I/O, fixed ; ; ||________ Not used ; ; ; ;----------------------------------------------; db 00001000b ; DMA1 memory+1 -> I/O, DMA1 edge trigged, ; ; DMA0 level trigged, no mem wait, no I/O wait ; ; ; ; 0000 1000 --- dcntl ; ; |||| ||||_ DMA1 mode ; ; |||| || 00: Mem+1 -> I/O ; ; |||| || 01: Mem-1 -> I/O ; ; |||| || 10: I/O -> mem+1 ; ; |||| || 11: I/O -> mem-1 ; ; |||| ||___ /DREQ0 edge/level trigged ; ; |||| |____ /DREQ1 edge/level trigged ; ; ||||______ I/O wait state insertion ; ; ||________ Memory wait state insertion ; ; ; ;----------------------------------------------; dma_table_length: equ $-dma_init_table ; This length is fixed to be 13h ; ;----------------------------------------------------------------------------; ; ESCC initialization table ; ;----------------------------------------------------------------------------; escc_init_table: ; ; ;----------------------------------------------; if sdlc ; SDLC: DMA, NRZ, no CRC, 8 bits/character,no ; ; DPLL, PCLK->BRG, baudrate = 1/4 PCLK, ; ; local loop-back. ; ;----------------------------------------------; clockHz: EQU 18432000 ; PLCK = 18.432 MHz ; baudRate: EQU 4608000 ; Data rate = 4.608 Mbps ; ; (The maximum baud rate is 1/4 of ; ; PCLK, 4.608 Mbaud.) ; DPLL: EQU 1 ; 1: DPLL is not used ; ; 16: DPLL with FM0, or FM1 ; ; 32: DPLL with NRZI ; time_const: EQU clockHz/baudRate/DPLL/2 - 2 ; Time Constant ; ;----------------------------------------------; db 9,11000000b ; Hardware reset both channels ; ; ; ; XX00 0000 --- WR9 ; ; |||| ||||_ VIS ; ; |||| |||__ NV ; ; |||| ||___ DLC ; ; |||| |____ MIE ; ; ||||______ Status high / status low ; ; |||_______ Software INTACK enable ; ; ||________ 00: No reset ; ; 01: Reset channel B ; ; 10: Reset channel A ; ; 11: Hardware reset ; ; ; ;----------------------------------------------; db 4,00100000b ; Select SDLC mode ; ; ; ; 00XX 0000 --- WR4 ; ; |||| ||||_ Parity enable ; ; |||| |||__ Parity Even / Odd ; ; |||| ||___ 00: Sync mode enable ; ; |||| 01: 1 stop bit ; ; |||| 10: 1.5 stop bits ; ; |||| 11: 2 stop bits ; ; ||||______ 00: 8-bit sync character ; ; || 01: 16-bit sync character ; ; || 10: SDLC mode (01111110 flag) ; ; || 11: External sync mode ; ; ||________ 00: Async x1 clock mode ; ; 01: Async x16 clock mode ; ; 10: Async x32 clock mode ; ; 11: Async x64 clock mode ; ; ; ;----------------------------------------------; db 7,01111110b ; Sync flag, 7E for SDLC ; ; ; ; XXXX XXXX --- WR7 ; ; |_______|_ Sync flag ; ; ; ;----------------------------------------------; db 10,10000000b ; CRC preset to 1, NRZ, flag idle, flag on ; ; underrun, no loop mode ; ; ; ; XXX0 XX00 --- WR10 ; ; |||| ||||_ 6-bit/8-bit sync ; ; |||| |||__ Loop mode ; ; |||| ||___ Abort/flag on underrun ; ; |||| |____ Mark/flag idle ; ; ||||______ Go active on poll ; ; |||_______ 00: NRZ ; ; | 01: NRZI ; ; | 10: FM1 ; ; | 11: FM0 ; ; |_________ CRC preset 1/0 ; ; ; ;----------------------------------------------; db 11,01010110b ; No crystal, /TRxC is BRG output, ; ; Tx clock = BRG, Rx clock = BRG. ; ; ; ; 0XXX X1XX --- WR11 ; ; |||| ||||_ 00: /TRxC out = Xtal output ; ; |||| || 01: /TRxC out = Transmit clock ; ; |||| || 10: /TRxC out = BRG output ; ; |||| || 11: /TRxC out = DPLL output ; ; |||| ||___ /TRxC output / input ; ; ||||_|____ 00: Tx clock = /RTxC pin ; ; ||| 01: Tx clock = /TRxC pin ; ; ||| 10: Tx clock = BRG output ; ; ||| 11: Tx clock = DPLL output ; ; |||_______ 00: Rx clock = /RTxC pin ; ; | 01: Rx clock = /TRxC pin ; ; | 10: Rx clock = BRG output ; ; | 11: Rx clock = DPLL output ; ; |_________ /RTxC xtal / no xtal ; ; ; ;----------------------------------------------; db 12,LOW time_const ; Load "Time Constant" to BRG ; ; ; ; XXXX XXXX --- WR12 ; ; |_______|_ Lower byte of Time Constant ; ; ; db 13,HIGH time_const ; XXXX XXXX --- WR13 ; ; |_______|_ Higher byte of Time Constant ; ; ; ;----------------------------------------------; db 14,00010111b ; Local loopback, DTR/REQ as /REQ for DMA,PCLK ; ; -> BRG, enable BRG. ; ; ; ; 0000 00XX --- WR14 ; ; | || ||||_ BRG enable ; ; | || |||__ BRG source: PCLK / /RTxC ; ; | || ||___ DTR//REQ function select ; ; | || |____ Auto echo ; ; | ||______ Local loop back ; ; |_|_______ 000: Null command ; ; 001: Enter search mode ; ; 010: Reset missing clock ; ; 011: Disable DPLL ; ; 100: DPLL source: BRG ; ; 101: DPLL source: /RTxC ; ; 110: DPLL operates in FM mode ; ; 111: DPLL operates in NRZI mode ; ; ; ;----------------------------------------------; if escc ; ESCC ; ;----------------------------------------------; db 15,00000001b ; Enable WR7' ; ; ; ; 0000 0101 --- WR15 ; ; |||| ||||_ WR7' SDLC feature enable ; ; |||| |||__ Zero count IE ; ; |||| ||___ SDLC FIFO enable ; ; |||| |____ DCD IE ; ; ||||______ Sync/hunt IE ; ; |||_______ CTS IE ; ; ||________ Tx underrun/EOM IE ; ; |_________ Break / abort IE ; ; ; ;----------------------------------------------; db 7,00101100b ; Enable Tx and Rx FIFO enhancements ; ; ; ; 0010 1000 --- WR7' ; ; |||| ||||_ Auto Tx flag ; ; |||| |||__ Auto EOM reset ; ; |||| ||___ Auto /RTS deactivation ; ; |||| |____ Rx FIFO interrupt level ; ; ||||______ /DTR//REQ timing mode ; ; |||_______ Tx FIFO interrupt level ; ; ||________ Extended read enable ; ; |_________ Not used, always 0 ; ; ; ; ; ;----------------------------------------------; endif ; endif ESCC ; ;----------------------------------------------; db 1,11100000b ; Enable W/REQ, select it for receive DMA /REQ ; ; disable all ESCC interrupts. ; ; ; ; 0001 0010 --- WR1 ; ; |||| ||||_ Ext interrupt enable ; ; |||| |||__ Tx interrupt enable ; ; |||| ||___ Parity is special condition ; ; ||||_|____ 00: Rx interrupt disable ; ; ||| 01: Rx int on 1st char or special ; ; ||| 10: Rx int on all char or special ; ; ||| 11: Rx int on special only ; ; |||_______ 0: W/REQ on transmit ; ; || 1: W/REQ on receive ; ; ||________ 0: W/REQ as /WAIT ; ; | 1: W/REQ as /REQ for DMA ; ; |_________ enable W/REQ ; ; ; ;----------------------------------------------; db 5,01100000b ; Transmit 8 bits/character ; ; ; ; 0110 0000 --- WR5 ; ; |||| ||||_ Tx CRC enable ; ; |||| |||__ RTS ; ; |||| ||___ CRC-16/SDLC ; ; |||| |____ Tx enable ; ; ||||______ Send break ; ; |||_______ 00: Tx 5 bits(or less)/character ; ; | 01: Tx 7 bits / character ; ; | 10: Tx 6 bits / character ; ; | 11: Tx 8 bits / character ; ; |_________ DTR ; ; ; ;----------------------------------------------; db 3,11000001b ; Enable Rx, Rx 8-bit/character. ; ; ; ; 1100 1001 --- WR3 ; ; |||| ||||_ Rx enable ; ; |||| |||__ Sync character load inhibit ; ; |||| ||___ Address search mode (SDLC) ; ; |||| |____ Rx CRC enable ; ; ||||______ Enter hunt mode ; ; |||_______ Auto enables ; ; ||________ 00: Rx 5 bits/character ; ; 01: Rx 7 bits/character ; ; 10: Rx 6 bits/character ; ; 11: Rx 8 bits/character ; ; ; ;----------------------------------------------------------------------------; else ; Async: DMA, 8-N-1, x1 clock mode, no CRC, no ; ; DPLL, PCLK->BRG, baudrate = 1/4 PCLK, ; ; local loop-back. ; ;----------------------------------------------; clockHz: EQU 18432000 ; PLCK = 18.432 MHz ; baudRate: EQU 4608000 ; Data rate = 4.608 Mbps ; ; (The maximum baud rate is 1/4 of ; ; PCLK, 4.608 Mbaud.) ; cMode: EQU 1 ; 1: Async x1 clock mode ; ; 16: Async x16 clock mode ; ; 32: Async x32 clock mode ; ; 64: Async x64 clock mode ; time_const: EQU clockHz/baudRate/cMode/2 - 2 ; Time Constant ; ;----------------------------------------------; db 9,11000000b ; Hardware reset both channels ; ; ; ; XX00 0000 --- WR9 ; ; |||| ||||_ VIS ; ; |||| |||__ NV ; ; |||| ||___ DLC ; ; |||| |____ MIE ; ; ||||______ Status high / status low ; ; |||_______ Software INTACK enable ; ; ||________ 00: No reset ; ; 01: Reset channel B ; ; 10: Reset channel A ; ; 11: Hardware reset ; ; ; ;----------------------------------------------; db 4,00000100b ; Async x1 clock, 1 stop bit, parity off ; ; ; ; 00XX 0000 --- WR4 ; ; |||| ||||_ Parity enable ; ; |||| |||__ Parity Even / Odd ; ; |||| ||___ 00: Sync mode enable ; ; |||| 01: 1 stop bit ; ; |||| 10: 1.5 stop bits ; ; |||| 11: 2 stop bits ; ; ||||______ 00: 8-bit sync character ; ; || 01: 16-bit sync character ; ; || 10: SDLC mode (01111110 flag) ; ; || 11: External sync mode ; ; ||________ 00: Async x1 clock mode ; ; 01: Async x16 clock mode ; ; 10: Async x32 clock mode ; ; 11: Async x64 clock mode ; ; ; ;----------------------------------------------; db 11,01010110b ; No crystal, /TRxC is BRG output, ; ; Tx clock = BRG, Rx clock = BRG. ; ; ; ; 0XXX X1XX --- WR11 ; ; |||| ||||_ 00: /TRxC out = Xtal output ; ; |||| || 01: /TRxC out = Transmit clock ; ; |||| || 10: /TRxC out = BRG output ; ; |||| || 11: /TRxC out = DPLL output ; ; |||| ||___ /TRxC output / input ; ; ||||_|____ 00: Tx clock = /RTxC pin ; ; ||| 01: Tx clock = /TRxC pin ; ; ||| 10: Tx clock = BRG output ; ; ||| 11: Tx clock = DPLL output ; ; |||_______ 00: Rx clock = /RTxC pin ; ; | 01: Rx clock = /TRxC pin ; ; | 10: Rx clock = BRG output ; ; | 11: Rx clock = DPLL output ; ; |_________ /RTxC xtal / no xtal ; ; ; ;----------------------------------------------; db 12,LOW time_const ; Load "Time Constant" to BRG ; ; ; ; XXXX XXXX --- WR12 ; ; |_______|_ Lower byte of Time Constant ; ; ; db 13,HIGH time_const ; XXXX XXXX --- WR13 ; ; |_______|_ Higher byte of Time Constant ; ; ; ;----------------------------------------------; db 14,00010111b ; Local loopback, DTR/REQ as /REQ for DMA,PCLK ; ; -> BRG, enable BRG. ; ; ; ; 0000 00XX --- WR14 ; ; | || ||||_ BRG enable ; ; | || |||__ BRG source: PCLK / /RTxC ; ; | || ||___ DTR//REQ function select ; ; | || |____ Auto echo ; ; | ||______ Local loop back ; ; |_|_______ 000: Null command ; ; 001: Enter search mode ; ; 010: Reset missing clock ; ; 011: Disable DPLL ; ; 100: DPLL source: BRG ; ; 101: DPLL source: /RTxC ; ; 110: DPLL operates in FM mode ; ; 111: DPLL operates in NRZI mode ; ; ; ;----------------------------------------------; if escc ; ESCC ; ;----------------------------------------------; db 15,00000001b ; Enable WR7' ; ; ; ; 0000 0001 --- WR15 ; ; |||| ||||_ WR7' SDLC feature enable ; ; |||| |||__ Zero count IE ; ; |||| ||___ SDLC FIFO enable ; ; |||| |____ DCD IE ; ; ||||______ Sync/hunt IE ; ; |||_______ CTS IE ; ; ||________ Tx underrun/EOM IE ; ; |_________ Break / abort IE ; ; ; ;----------------------------------------------; db 7,00101000b ; Enable Tx and Rx FIFO enhancements ; ; ; ; 0010 1000 --- WR7' ; ; |||| ||||_ Auto Tx flag ; ; |||| |||__ Auto EOM reset ; ; |||| ||___ Auto /RTS deactivation ; ; |||| |____ Rx FIFO interrupt level ; ; ||||______ /DTR//REQ timing mode ; ; |||_______ Tx FIFO interrupt level ; ; ||________ Extended read enable ; ; |_________ Not used, always 0 ; ; ; ;----------------------------------------------; endif ; endif ESCC ; ;----------------------------------------------; db 1,11100000b ; Enable W/REQ, select it for receive DMA /REQ ; ; disable all ESCC interrupts. ; ; ; ; 0001 0010 --- WR1 ; ; |||| ||||_ Ext interrupt enable ; ; |||| |||__ Tx interrupt enable ; ; |||| ||___ Parity is special condition ; ; ||||_|____ 00: Rx interrupt disable ; ; ||| 01: Rx int on 1st char or special ; ; ||| 10: Rx int on all char or special ; ; ||| 11: Rx int on special only ; ; |||_______ 0: W/REQ on transmit ; ; || 1: W/REQ on receive ; ; ||________ 0: W/REQ as /WAIT ; ; | 1: W/REQ as /REQ for DMA ; ; |_________ enable W/REQ ; ; ; ;----------------------------------------------; db 5,01100000b ; Transmit 8 bits/character ; ; ; ; 0110 0000 --- WR5 ; ; |||| ||||_ Tx CRC enable ; ; |||| |||__ RTS ; ; |||| ||___ CRC-16/SDLC ; ; |||| |____ Tx enable ; ; ||||______ Send break ; ; |||_______ 00: Tx 5 bits(or less)/character ; ; | 01: Tx 7 bits / character ; ; | 10: Tx 6 bits / character ; ; | 11: Tx 8 bits / character ; ; |_________ DTR ; ; ; ;----------------------------------------------; db 3,11000001b ; Enable Rx, Rx 8-bit/character ; ; ; ; 1100 1001 --- WR3 ; ; |||| ||||_ Rx enable ; ; |||| |||__ Sync character load inhibit ; ; |||| ||___ Address search mode (SDLC) ; ; |||| |____ Rx CRC enable ; ; ||||______ Enter hunt mode ; ; |||_______ Auto enables ; ; ||________ 00: Rx 5 bits/character ; ; 01: Rx 7 bits/character ; ; 10: Rx 6 bits/character ; ; 11: Rx 8 bits/character ; ; ; ;----------------------------------------------------------------------------; endif ; endif SDLC-Async ; ;----------------------------------------------; escc_table_length: equ $-escc_init_table ; Calculate table length ; ;----------------------------------------------------------------------------; ; Reserve data space ; ;----------------------------------------------------------------------------; tx_buff: ; Reserve Tx buffer ; ;----------------------------------------------; db "\r\n\nThe " ; ; ;----------------------------------------------; if escc ; ESCC ; db "ESCC " ; ; else ; SCC ; db "SCC " ; ; endif ; ; ;----------------------------------------------; if channel_a ; Channel A ; db "channel A " ; ; else ; Channel B ; db "channel B " ; ; endif ; ; ;----------------------------------------------; db "sent and received this message in " ; ;----------------------------------------------; if sdlc ; SDLC ; db "SDLC " ; ; else ; Async ; db "ASYNC " ; ; endif ; ; ;----------------------------------------------; db "mode\r\nwith DMA transfers.\r\n" ; ; db 0 ; End with 0. ; ;----------------------------------------------; buff_length: equ $-tx_buff ; Calculate the length of tx_buff ; ;----------------------------------------------------------------------------; zero: ; ; ds 1 ; Reserve 1 byte for temp ; done_flag: ; ; ds 1 ; Reserve 1 byte for done_flag ; ;----------------------------------------------------------------------------; rx_buff: ; Reserve Rx buffer with same length as Tx ; ds buff_length ; buffer. ; ;----------------------------------------------------------------------------; ds 20h ; Reserve at least 20h bytes for stack. ; align 100h ; ; top_of_stack: ; ; ;============================================================================; end start ; End of assembly code ; ;============================================================================;