Z16C3010AEG
Features
- Two Independent 0-to-10 Mbps Full-Duplex Channels, each with Two Baud Rate Generators and One digital phase-locked loop (DPLL) for Clock Recovery
- 32-byte Data FIFO’s for each Receiver and Transmitter
- 110 ns Bus Cycle Time, 16-bit Data Bus Bandwidth
- Multi-Protocol Operation under Program Control with Independent Mode Selection for Receiver and Transmitter
- External Character Sync Mode for Receive
- HDLC/SDLC Mode with Eight-Bit Address Compare, Extended Address Field Option, 16- or 32-bit CRC, Programmable Idle Line Condition, Optional Preamble Transmission and Loop Mode
- DMA Interface with Separate Request and Acknowledge for Each Receiver and Transmitter
- Channel Load Command for DMA Controlled Initialization
- Flexible Bus Interface for Direct Connection to Most Microprocessors, User Programmable for 8 or 16 Bits Wide, Directly Supports 680X0 Family or 8X86 Family Bus Interfaces
- Low Power CMOS
- 68-Pin PLCC/100-Pin VQFP Packages
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