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Hi,
Tribute to the Z8
Back in 2002, I've the idea to design a SW able to display real time video (in the spirit of the famous ZX81).
Starting from a Z85E30 @12Mhz, i can reach a video memory of 48x28 pixels (almost square) @ 50hz frame.
1) Video generation
P0.0 was used as sync generetor
P2.0 was used as video pixel data
The two output are added to obtain the 3 level signal (through 75 Ohms)
P0.0----R----+----> video output
P2.0----R----+---- 75----GND
So
P0.0 P2.0
0 0 => Top line level (infra black)
1 0 => video black level
1 1 => video white level
The video is generated through a careful timing implementtation.
The CPU spends 80% of the time to generate video. During the beginning the image (invisible line) , a background SW is executed (a simple game)
The central piece of code is the pixel generation;
To obtain 48 pixels/line, you have to output continuously one pixel per µS.
So I've usrd the tricks :
6 bytes pointers to allow 48 pixels
The use of direct port rotation to output the pixel;
it looks like that :
rVid is P2 as output port
ra,rb,rc,rd,re,rf are consecutive byte pointer in the video memory
char
nop
ld rSync,#BAS ;generate Sync low
nop
nop
nop
nop
ld rSync,#HAUT ; generate Sync high
nop
nop
nop
nop
nop
ligne ; 48 pixels = 48*1=48µs
nop
ld rVid,@ra ; 8 pixels loading bit 0 output
rr rVid ; output bit 1
rr rVid
rr rVid
rr rVid
rr rVid
rr rVid
rr rVid ; bit 8
ld rVid,@rb ; next 8 pixels in video memory, b0 output
rr rVid
rr rVid
rr rVid
rr rVid
rr rVid
rr rVid
rr rVid
ld rVid,@rc ; 8 pixels
rr rVid
rr rVid
rr rVid
rr rVid
rr rVid
rr rVid
rr rVid
ld rVid,@rd ; 8 pixels
rr rVid
rr rVid
rr rVid
rr rVid
rr rVid
rr rVid
rr rVid
ld rVid,@re ; 8 pixels
rr rVid
rr rVid
rr rVid
rr rVid
rr rVid
rr rVid
rr rVid
ld rVid,@rf ; 8 pixels
rr rVid
rr rVid
rr rVid
rr rVid
rr rVid
rr rVid
rr rVid
clr rVid ; to prepare video horizontal blanking
djnz r9,char ; the sequence is repeated 10 times per pixel, including the SYNC pulse generation
Then ra,...,rf are incremented by 6 and the process is repeated 28 times.
swap r9 ; accomodate different execution time
;
ld rSync,#BAS ; µSync low
ld r9,#10 ; 10 lines again
add ra,r4 ; ra pointer move from 6 bytes
add rb,r4 ; rb pointer move from 6 bytes
add rc,r4 ; rc pointer move from 6 bytes
ld rSync,#HAUT ; Sync high
add rd,r4 ; rd pointer move from 6 bytes
add re,r4 ; re pointer move from 6 bytes
add rf,r4 ; rf pointer move from 6 bytes
djnz r8,ligne ; 28 times
Then the end of frame is built, blanking pulse and invisible top line.
During the upper non visible line, the SW through INT and timer generates SYNC pulse only. During this phase the signal has a small jitter because of the non constant execution of instruction, but internal PLL of television seems to overcome that.
The back ground SW is then running. I've built for demo a small gamme brick and a ball moving around with a small horizontal racket.
Attach complete source in french (nobody is perfect).
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