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The issue for RUN/STEP trouble in DEBUG seems to be related to the clock setting. I am using the same system board for this exploration that I used for an existing 24-bit project. I had used the same target file settings, but there is some dependency that i don't understand while using an assembly project.
I am using the dev kit board so we have the same hardware. I made the project work with the PLL turned off and the system clock set to 5MHz, OR I left the PLL turned on with the settings of 50MHz/5MHz and the 'Change ZDI clock on Request' unchecked.
I'd like to better understand the dependency involved there.
Excerpt from ZDS help regarding pll settings
To use the phase-locked loop, select the Phase-Locked Loop button, enter the clock frequency in the System Clock Frequency (Hz) field, enter the oscillator frequency in the Oscillator Frequency (Hz) field, select a charge pump current, and select a lock criteria.
The eZ80F91 device contains a Phase-Locked Loop (PLL) module, the output of which can be used as the system clock. This allows the application to run at 50 MHz with an oscillator frequency between 1 and 10 MHz. Since the system defaults to using the oscillator upon power-on or hardware reset, the application program must enable and select the PLL as the source of the system clock. This also requires the ZDI clock frequency to change if a debug session is started so that a reliable connection can be maintained. ZDS automatically changes the rate after the first Reset or Go command is invoked and the Change ZDI Clock Upon Reset check box has been selected.
ZDS assumes that the system clock change occurs somewhere after reset and before the main() routine. For information about how to set up the charge pump current and lock criteria, see the "Phase Locked Loop" chapter of the eZ80F91 MCU Product Specification (PS0192).
I see two areas to investigate, when ZDS automatically changes rate and when ZDS assumes rate has changed.
Tom, your comment about running into this before helped me remember similar trouble during my first exposure with this dev system. I had not selected a correct system clock value. Also, the ZSFP utility uses the same target file format, but needs the system clock set to 5Mhz instead of 50 Mhz. ( I see now, how that happened )
Alex, thank you for the link to your RTOS project, I only explored as far as the startup. It was a big help to use one of your sample projects to investigate my settings. The documentation is nicely done and the code is very organized.
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