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#1859
To Receive 9-bit data from UART 2 Weeks, 4 Days ago Karma: 0
Hi,
I have written following initialization code to receive 9-bit data from UART0 of ez80Acclaim ez80F91 micro-controller. However I am unable to receive correct data.
Code:
//////////////////////////// Initialize 9 Bit Serial Port 1 & Interrupt ///////////////////////////////////////////
void uart0_init(void)
{
    unsigned short brg;

    brg = SysClkFreq/(16 * 19200);

set_vector(VECTOR_UART0,isr_uart0);

UART0_LCTL=0x80; // select dlab to access baud rate generators

    UART0_BRG_L = (brg & (unsigned short)0x00FF);
    UART0_BRG_H = (brg & (unsigned short)0xFF00) >> (unsigned short)8;

UART0_LCTL=0x00; // disable dlab
UART0_FCTL=0x06; // clear tx fifo, clear rx fifo, fifo enable
UART0_LCTL=0x1B; // enable 9bit and set 8,1
UART0_MCTL=0x20; // Enable Multi drop mode
UART0_IER=0x05; // rx int enable, master int enable.
}


Following is the code of the interrupt service routine to receive the data.
Code:
/*********************** ISR Serial Interrupt with 9 bit **************************************/

#pragma interrupt
void isr_uart0(void) 
{
unsigned char TEMP=UART0_LSR;
    
  if (TEMP & 0x01) // If this is true the we have just plan old 8 bit data 
{
wr2rx_fifo_C(UART0_RBR,0x00);  //saving the data to rx fifo
}

if (TEMP & 0x40) // If this is true then we Transmit holding register is idle
{
while(UART0_LSR & 0x40) //updated 03-02-2010 // TX int
{
if(rdftx_fifo_C()==1)  // reading from the tx_fifo
{ // and we still have stuff to send ...
if(tx_fifo_9bit==1)
{
UART0_LCTL=0x1B; // setting 9th bit as adress
}
UART0_MCTL=0x20; // Enable Multi drop mode
UART0_THR=tx_fifo_byte; //Sending 8-bit Data
}
else
{
//UART0_LCTL=0x1B;
//UART0_MCTL=0x20;
UART0_MCTL=0x00;
UART0_IER=0x05; // disable tx interrupts
break;
}
}
txd_flag=0;
}
}


Please help asap.
Masood ur Rehman (User)
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#1860
Re:To Receive 9-bit data from UART 2 Weeks, 4 Days ago Karma: 0
I have this example of an eZ80 uart ISR from working code where I talk with multiple Z8's in multidrop mode.

Code:
void nested_interrupt Uart_485_ISR( void )
{
uint8_t c;
char iir ;

uint8_t statusa;
uint8_t mdstat; 
volatile unsigned short cnt;

iir = UART1_IIR;


if( 0 == (iir & UART_IIR_INTBIT) ) //! See if there is any active interrupt source and handle it.
{
if( UART_IIR_TRANSCOMPLETE == (iir & UART_IIR_ISCMASK) )
{
if ( i1r )
{
if (  (i1r->slen == 0) || ( i1r->sidx == i1r->slen ) )
{
i1r->tx_complete = 1;
UART1_IER &= ~UART_IER_TRANSCOMPLETEINT; 

return;
}
#if PKT_MDM
if (i1r->sidx == i1r->leadin_addr_idx)
{
while ( ! (UART1_LSR & UART_LSR_TEMT) )
;
UART1_LCTL &= ~UART_LCTL_EPS;  // resets bit after byte sent
}
else
{
UART1_LCTL |= UART_LCTL_EPS;  // resets bit after byte sent
}
#endif

for (cnt = 1; cnt < 60; cnt++)
  ;
UART1_THR = i1r->sbuf[i1r->sidx++];
}
}

if( UART_IIR_RDR == (iir & UART_IIR_ISCMASK) )
{
if ( i1r )
{

mdstat = (UART1_LSR & UART_LSR_PE);  // set to TRUE if 9th bit found
c = UART1_RBR;

if ( i1r )
{
#if PKT_MDM
if (mdstat)     // check if the MDMD addr bit is set
i1r->state = PKT_STATE_ADDRESS; // next byte is the address 
pkt_byte_rx( i1r, c );  // send this byte to the queue for the state machine
}
#endif


}
}
}

}


mdstat is set whenever the 9th bit is detected.
mr (User)
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#1861
Re:To Receive 9-bit data from UART 2 Weeks, 3 Days ago Karma: 0
Hi Mr,
Are these two different variables iir and i1r.
Masood ur Rehman (User)
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#1862
Re:To Receive 9-bit data from UART 2 Weeks, 3 Days ago Karma: 0
Yes, iir is a local variable used only to store the status of UART1_II as I enter the ISR. The status gives me the reason the ISR was triggered.

ir is a pointer to a structure that implements my queue and state machine variables. The lines with ir can all be considered application specific and can be substituted with code for your system.

I forgot to mention that your initialization seem the same as mine except that I use the sequence:
Code:
   UART0_FCTL = 0x00; // clear FIFO logic
UART0_FCTL = 0x01; // turn on FIFO first
UART0_FCTL = 0x07; // then enable xmit, rcv & FIFOs

because the specifications seemed to suggest multiple steps for enable FIFO reliably.
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